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| _______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 general description the max7360 i 2 c-interfaced peripheral provides micro- processors with management of up to 64 key switches, with an additional eight led drivers/gpios that feature constant-current, pwm intensity control, and rotary switch control options. the key-switch drivers interface with metallic or resis - tive switches with on-resistances up to 5k i . key inputs are monitored statically, not dynamically, to ensure low-emi operation. the max7360 features autosleep and autowake modes to further minimize the power consumption of the device. the autosleep feature puts the device in a low-power state (1 f a typ) after a sleep timeout period. the autowake feature configures the max7360 to return to normal operating mode from sleep upon a keypress. the key controller debounces and maintains a fifo of keypress and release events (including autorepeat, if enabled). an interrupt ( intk ) output can be configured to alert keypresses, as they occur, or at maximum rate. there are eight open-drain i/o ports, which can be used to drive leds. the maximum constant-current level for each open-drain port is 20ma. the intensity of the led on each open-drain port can be individually adjusted through a 256-step pwm control. an input port pair (port6, port7) can be configured to accept 2-bit gray code inputs from a rotary switch. in addition, if not used for key-switch control, up to six column pins can be used as general-purpose open-drain outputs (gpos) for led drive or logic control. the max7360 is offered in a 40-pin (5mm x 5mm) thin qfn package with an exposed pad, and a small 36-bump wafer level package (wlp) for cell phones, pocket pcs, and other portable consumer electronic applications. the max7360 operates over the -40 n c to +85n c extended temperature range. applications cell phones pdas handheld games portable consumer electronics printers instrumentation features s integrated esd protection 8kv iec 61000-4-2 contact discharge 15kv iec 61000-4-2 air-gap discharge s +14v tolerant, open-drain i/o ports capable of constant-current led drive s rotary switch-capable input pair (port6, port7) s 256-step pwm individual led intensity control s individual led blink rates and common led fade in/out rates from 256ms to 4096ms s fifo queues up to 16 debounced key events s user-configurable key debounce (9ms to 40ms) s keyscan uses static matrix monitoring for low emi operation s +1.62v to +3.6v operation s monitors up to 64 keys s key-switch interrupt (intk) on each debounced event/fifo level, or end of definable time period s port interrupt (inti) for input ports for special-key functions s 400kbps, +5.5v tolerant 2-wire serial interface with selectable bus timeout s four i 2 c address choices 19-4566; rev 1; 8/10 simplfied block diagram + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. pin configurations appear at end of data sheet. ordering information part temp range pin-package max7360etl+ -40c to +85c 40 tqfn-ep* max7360ewx+ -40c to +85c 36 wlp max7360 ad0 port7 port6 port0 col_(8x) row_(8x) intk inti sda scl rotary switch +14v 8 x 8 to fc +1.8v evaluation kit available
i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 2 ______________________________________________________________________________________ stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ............................................................. -0.3v to +4v col0Ccol7, row0Crow7 to gnd ...................... -0.3v to +4v sda, scl, ad0, inti, intk to gnd ........................ -0.3v to +6v port0Cport7 to gnd ......................................... -0.3v to +16v all other pins to gnd ................................ -0.3v to (v cc + 0.3v) dc current on port0Cport7, col2Ccol7 .................... 25ma gnd current ....................................................................... 80ma continuous power dissipation (t a = +70nc) 40-pin tqfn (derate 22.2mw/nc above +70nc) ....... 1777mw 36-bump wlp (derate 21.7mw/nc above +70nc) .... 1739mw junction-to-case thermal resistance (b jc ) (note 1) 40-pin tqfn .................................................................. 2nc/w 36-bump wlp ................................................................... n/a junction-to-ambient thermal resistance (b ja ) (note 1) 40-pin tqfn ................................................................ 45nc/w 36-bump wlp ............................................................. 46nc/w operating temperature range .......................... -40nc to +85nc junction temperature ..................................................... +150nc storage temperature range ............................ -65nc to +150nc esd protection human body model (r d = 1.5ki, c s = 100pf) all pins ............................................................................. q2kv iec 61000-4-2 (r d = 330i, c s = 150pf) contact discharge row0Crow7, col0Ccol7, port0Cport7 to gnd .... q8kv air-gap discharge row0Crow7, col0Ccol7, port0Cport7 to gnd .. q15kv lead temperature (tqfn only, soldering, 10s) .............. +300nc soldering temperature (reflow) ....................................... +260nc electrical characteristics (v cc = +1.62v to +3.6v, t a = -40 n c to +85n c, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25 n c.) (notes 2, 3) absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a single- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. parameter symbol conditions min typ max units operating supply voltage v cc 1.62 3.3 3.6 v external supply voltage port0Cport7 v port_ 14 v operating supply current i cc all key switches open, oscillator running, col2Ccol7 configured as key switches, v port _ = v cc 34 50 fa n keys pressed 34 + 20 x n sleep-mode supply current i sl 1.3 3 fa key-switch source current i key 20 35 fa key-switch source voltage v key 0.43 0.5 v key-switch resistance r key (note 4) 5 ki startup time from shutdown t start 2 2.4 ms output low voltage col2Ccol7 v ol i sink = 10ma 0.5 v oscillator frequency (pwm clock) f osc t a = +25nc, v cc = +2.61v 125 128 131 khz t a = t min to t max , v cc p 3.6v 102 164 oscillator frequency variation df osc t a = +25nc -6 +8.5 % key-scan frequency f key derived from oscillator clock 64 khz i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +1.62v to +3.6v, t a = -40 n c to +85n c, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25 n c.) (notes 2, 3) parameter symbol conditions min typ max units gpio specifications input high voltage port0Cport7 v ih 0.7 x v cc v input low voltage port0Cport7 v il 0.3 x v cc v input leakage current port0Cport7 i in v in p v cc -0.25 +0.25 fa v cc < v in -1 +5 output low voltage port0Cport7 v ol i sink < 20ma 0.6 v input capacitance port0Cport7 20 pf 10ma port sinking current port0Cport7 v cc = +1.62v to +3.6v, t a = +25nc 8.55 11.52 ma v cc = +3.3v, v ol = +1v 8.67 9.76 10.51 20ma port sinking current port0Cport7 v cc = +1.62v to +3.6v, t a = +25nc 19.40 21.33 ma v cc = +3.3v, v ol = +1v 19.55 20 20.69 port sink current variation v cc = +3.3v, v ol = +1v, t a = +25nc, 20ma output mode +q1.5 +q2.4 % output logic-low voltage inti, intk i sink = 10ma 0.6 v pwm frequency f pwm derived from oscillator clock 500 hz serial-interface specifications input high voltage sda, scl, ad0 v ih 0.7 x v cc v input low voltage sda, scl, ad0 v il 0.3 x v cc v input leakage current sda, scl, ad0 i in v in p v cc -0.25 +0.25 fa v in > v cc -0.5 +0.5 output low voltage sda v ol i sink = 6ma 0.6 v input capacitance sda, scl, ad0 c in 10 pf i 2 c timing specifications scl serial-clock frequency f scl bus timeout disabled 0 400 khz bus free time between a stop and start condition t buf 1.3 fs hold time (repeated) start condition t hd, sta 0.6 fs repeated start condition setup time t su, sta 0.6 fs stop condition setup time t su, sto 0.6 fs i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 4 ______________________________________________________________________________________ electrical characteristics (continued) (v cc = +1.62v to +3.6v, t a = -40 n c to +85n c, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25 n c.) (notes 2, 3) note 2: all parameters are tested at t a = +25 n c. specifications over temperature are guaranteed by design. note 3: all digital inputs at v cc or gnd. note 4: guaranteed by design. note 5: a master device must provide a hold time of at least 300ns for the sda signal (referred to v il of the scl signal) to bridge the undefined region of scls falling edge. note 6: c b = total capacitance of one bus line in pf. t r and t f measured between +0.3v cc and +0.7v cc . note 7: i sink 6ma. note 8: input filters on the sda, scl, and ad0 inputs suppress noise spikes less than 50ns. parameter symbol conditions min typ max units data hold time t hd, dat (note 5) 0.9 fs data setup time t su, dat 100 ns scl clock low period t low 1.3 fs scl clock high period t high 0.7 fs rise time of both sda and scl signals, receiving t r (notes 4, 6) 20 + 0.1c b 300 ns fall time of both sda and scl signals, receiving t f (notes 4, 6) 20 + 0.1c b 300 ns fall time of sda signal, transmitting t f, tx (notes 4, 7) 20 + 0.1c b 250 ns pulse width of spike suppressed t sp (notes 4, 8) 50 ns capacitive load for each bus line c b (note 4) 400 pf i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 _______________________________________________________________________________________ 5 typical operating characteristics (v cc = +2.5v, t a = +25 n c, unless otherwise noted.) gpo output low voltage vs. sink current (col2?col7) max7360 toc01 sink current (ma) output voltage (mv) 15 10 5 50 100 150 200 250 0 0 20 t a = +85 n c t a = +25 n c t a = -40 n c v cc = 2.4v gpo output low voltage vs. sink current (col2?col7) max7360 toc02 sink current (ma) output voltage (mv) 15 10 5 50 100 150 200 250 0 0 20 t a = +25c t a = -40c v cc = 3.0v t a = +85c gpo output low voltage vs. sink current (col2?col7) max7360 toc03 sink current (ma) output voltage (mv) 15 10 5 50 100 150 200 250 0 0 20 t a = +25c t a = -40c v cc = 3.6v t a = +85c key-switch source current vs. supply voltage max7360 toc05 supply voltage (v) key-switch source current (a) 2.8 2.4 2.0 17.7 17.8 17.5 17.6 17.9 18.0 18.1 18.2 18.3 18.4 17.4 1.6 3.6 3.2 v col0 = o t a = -40 n c, +25 n c t a = +25 n c t a = -40 n c t a = -40 n c, +85 n c t a = +85 n c shutdown supply current vs. supply voltage max7360 toc06 supply voltage (v) shutdown supply current (a) 2.8 2.4 2.0 1.0 0.5 1.5 2.0 2.5 3.0 0 1.6 3.6 3.2 t a = -40 n c t a = +25 n c t a = +85 n c constant-current gpio output sink current vs. output voltage max7360 toc07 output voltage (v) sink current (ma) 1.5 2.0 1.0 0.5 5 10 15 20 25 0 0 3.0 2.5 t a = -40 n c v cc = 2.4v t a = +25 n c t a = +85 n c constant-current gpio output sink current vs. output voltage max7360 toc09 output voltage (v) sink current (ma) 1.5 2.0 1.0 0.5 5 10 15 20 25 0 0 3.0 2.5 t a = -40 n c v cc = 3.6v t a = +25 n c t a = +85 n c constant-current gpio output sink current vs. output voltage max7360 toc08 output voltage (v) sink current (ma) 1.5 2.0 1.0 0.5 5 10 15 20 0 0 3.0 2.5 25 v cc = 3.0v t a = -40 n c t a = +25 n c t a = +85 n c supply current vs. supply voltage max7360 toc04 supply voltage (v) supply current (a) 2.8 2.4 2.0 25 20 30 35 40 45 15 1.6 3.6 3.2 t a = +85 n c autosleep = off t a = -40 n c t a = +25 n c i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 6 ______________________________________________________________________________________ pin description pin name function tqfn wlp 1 a6 row0 row input from key matrix. leave row0 unconnected or connect to gnd if unused. 2 b6 row1 row input from key matrix. leave row1 unconnected or connect to gnd if unused. 3 c4 row2 row input from key matrix. leave row2 unconnected or connect to gnd if unused. 4 c6 row3 row input from key matrix. leave row3 unconnected or connect to gnd if unused. 5, 15, 25, 35 b4, c5, d2, e4 gnd ground 6 d6 row4 row input from key matrix. leave row4 unconnected or connect to gnd if unused. 7 d5 row5 row input from key matrix. leave row5 unconnected or connect to gnd if unused. 8 e6 row6 row input from key matrix. leave row6 unconnected or connect to gnd if unused. 9 d4 row7 row input from key matrix. leave row7 unconnected or connect to gnd if unused. 10, 20, 27, 30, 40 c2 n.c. no connection. not internally connected. leave unconnected. 11 f6 col0 column output to key matrix. leave col0 unconnected if unused. 12 e5 col1 column output to key matrix. leave col1 unconnected if unused. 13 f5 col2 column output to key matrix. leave col2 unconnected if unused. col2 can be configured as a gpo (see table 9 in the register tables section). 14 f4 col3 column output to key matrix. leave col3 unconnected if unused. col3 can be configured as a gpo (see table 9 in the register tables section). 16 f3 col4 column output to key matrix. leave col4 unconnected if unused. col4 can be configured as a gpo (see table 9 in the register tables section). 17 e3 col5 column output to key matrix. leave col5 unconnected if unused. col5 can be configured as a gpo (see table 9 in the register tables section). 18 f2 col6 column output to key matrix. leave col6 unconnected if unused. col6 can be configured as a gpo (see table 9 in the register tables section). 19 f1 col7 column output to key matrix. leave col7 unconnected if unused. col7 can be configured as a gpo (see table 9 in the register tables section). 21 e2 sda i 2 c-compatible, serial-data i/o 22 e1 scl i 2 c-compatible, serial-clock input 23 d3 intk active-low key-switch interrupt output. intk is open drain and requires a pullup resistor. i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 _______________________________________________________________________________________ 7 pin description (continued) pin name function tqfn wlp 24 d1 inti active-low gpi interrupt output. inti is open drain and requires a pullup resistor. 26 c1 v cc positive supply voltage. bypass v cc to gnd with a 0.1ff or higher ceramic capacitor. 28 b1 ad0 address input. ad0 selects up to four device slave addresses (table 3). 29 a1 i.c. internally connected. connect to gnd for normal operation. 31 b2 port0 gpio port. open-drain i/o rated at +14v. port0 can be configured as a constant- current output. 32 a2 port1 gpio port. open-drain i/o rated at +14v. port1 can be configured as a constant- current output. 33 b3 port2 gpio port. open-drain i/o rated at +14v. port2 can be configured as a constant- current output. 34 a3 port3 gpio port. open-drain i/o rated at +14v. port3 can be configured as a constant- current output. 36 a4 port4 gpio port. open-drain i/o rated at +14v. port4 can be configured as a constant- current output. 37 c3 port5 gpio port. open-drain i/o rated at +14v. port5 can be configured as a constant- current output. 38 a5 port6 gpio port. open-drain i/o rated at +14v. port6 can be configured as a constant- current output, or a rotary switch input. 39 b5 port7 gpio port. open-drain i/o rated at +14v. port7 can be configured as a constant- current output, or a rotary switch input. ep exposed pad (tqfn only). ep is internally connected to gnd. connect ep to a ground plane to increase thermal performance. i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 8 ______________________________________________________________________________________ functional block diagram detailed description the max7360 is a microprocessor peripheral low-noise key-switch controller that monitors up to 64 key switches with optional autorepeat, and key events that are pre - sented in a 16-byte fifo. the max7360 also features eight open-drain gpios configured for digital i/o or constant-current output for led applications up to +14v. the max7360 features an automatic sleep mode and automatic wakeup that further reduce supply current consumption. the max7360 can be configured to enter sleep mode after a programmable time following a key event. the fifo content is maintained and can be read in sleep mode. the max7360 does not enter autosleep when a key is held down. the autowake feature takes the max7360 out of sleep mode following a keypress event. enable/disable autosleep and autowake through the configuration register (table 8). to prevent overloading the microprocessor with too many interrupts, interrupt requests are issued on a programmable number of fifo entries, and/or after a set period of time (table 10). the key-switch status is checked by reading the key-switch fifo. a 1-byte read access returns both the next key event in the fifo (if there is one) and the fifo status. intk functions as an open-drain general-purpose output (gpo) capable of driving an led if key-switch interrupts are not required. up to six of the key-switch outputs function as open- drain gpos capable of driving additional leds when the application requires fewer keys to be scanned. for each key-switch output used as a gpo, the number of monitored key switches reduces by eight. initial power-up on power-up, all control registers are set to power-up values and the max7360 is in sleep mode (table 1). 128khz oscillator por bus timeout i 2 c interface control registers fifo key scan current source column drives open- drain row drives column enable gpo enable row enable current detect col0 col1 col2* col3* col4* col5* col6* col7* pwm gpio logic port gpio and constant- current led drive led enable gpio enable gpio input port0 port1 port2 port3 port4 port5 port6 port7 row0 row1 row2 row3 row4 row5 row6 row7 inti intk sda scl ad0 *gpo max7360 rotary i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 _______________________________________________________________________________________ 9 table 1. register address map and power-up condition address code (hex) read/ write power-up value (hex) register function description 0x00 read only 0x3f keys fifo read fifo key-scan data out 0x01 r/w 0x0a configuration power-down, key-release enable, autowakeup, and i 2 c time - out enable 0x02 r/w 0xff debounce key debounce time settling and gpo enable 0x03 r/w 0x00 interrupt key-switch interrupt intk frequency setting 0x04 r/w 0xfe gpo col2Ccol7 and intk gpo control 0x05 r/w 0x00 key repeat delay and frequency for key repeat 0x06 r/w 0x07 sleep idle time to autosleep 0x40 r/w 0x00 gpio global con - figuration rotary switch, gpio standby, gpio reset, fade 0x41 r/w 0x00 gpio control port0Cport7 input/output control 0x42 r/w 0x00 gpio debounce port0Cport7 debounce time setting 0x43 r/w 0xc0 gpio constant- current setting port0Cport7 constant-current output setting 0x44 r/w 0x00 gpio output mode port0Cport7 output mode control 0x45 r/w 0x00 common pwm common pwm duty-cycle setting 0x46 r/w 0x00 rotary switch con - figuration rotary switch interrupt frequency and debounce time setting 0x48 read only 0x00 i 2 c timeout flag i 2 c timeout since last por 0x49 read only 0xff gpio input register port0Cport7 input values 0x4a read only 0x00 rotary switch count switch cycles since last read 0x50 r/w 0x00 port0 pwm port0 individual duty-cycle setting 0x51 r/w 0x00 port1 pwm port1 individual duty-cycle setting 0x52 r/w 0x00 port2 pwm port2 individual duty-cycle setting 0x53 r/w 0x00 port3 pwm port3 individual duty-cycle setting 0x54 r/w 0x00 port4 pwm port4 individual duty-cycle setting 0x55 r/w 0x00 port5 pwm port5 individual duty-cycle setting 0x56 r/w 0x00 port6 pwm port6 individual duty-cycle setting 0x57 r/w 0x00 port7 pwm port7 individual duty-cycle setting 0x58 r/w 0x00 port0 configuration port0 interrupt, pwm mode control and blink period setting 0x59 r/w 0x00 port1 configuration port1 interrupt, pwm mode control and blink period setting 0x5a r/w 0x00 port2 configuration port2 interrupt, pwm mode control and blink period setting 0x5b r/w 0x00 port3 configuration port3 interrupt, pwm mode control and blink period setting 0x5c r/w 0x00 port4 configuration port4 interrupt, pwm mode control and blink period setting 0x5d r/w 0x00 port5 configuration port5 interrupt, pwm mode control and blink period setting 0x5e r/w 0x00 port6 configuration port6 interrupt, pwm mode control and blink period setting 0x5f r/w 0x00 port7 configuration port7 interrupt, pwm mode control and blink period setting i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 10 _____________________________________________________________________________________ key-scan controller key inputs are scanned statically, not dynamically, to ensure low-emi operation. as inputs only toggle in response to switch changes, the key matrix can be routed closer to sensitive circuit nodes. the key-scan controller debounces and maintains a fifo of keypress and release events (including autorepeated keypresses, if autorepeat is enabled). table 2 shows the key-switch order. the user-programmable key-switch debounce time, and autosleep timer, is derived from the 64khz clock, which in turn is derived from the 128khz oscillator. time delay for autorepeat and key-switch interrupt is based on the key-switch debounce time. keys fifo register (0x00) the keys fifo register contains the information pertaining to the status of the keys fifo, as well as the key events that have been debounced (see table 7 in the register tables section). bits d0Cd5 denote which of the 64 keys have been debounced and the keys are numbered as in table 2. d7 indicates if there is more data in the fifo, except when d5:d0 indicate key 63 or key 62. when d5:d0 indicate key 63 or key 62, the host should read one more time to determine whether there is more data in the fifo. use key 62 and key 63 for rarely used keys. d6 indicates if it is a keypress or release event, except when d5:d0 indicate key 63 or key 62. reading the key-scan fifo clears the interrupt intk depending on the setting of bit d5 in the configuration register (0x01). configuration register (0x01) the configuration register controls the i 2 c bus timeout feature, enables key-release detection, enables autowake, and determines how intk is deasserted. write to bit d7 to put the max7360 into sleep mode or operating mode. autosleep and autowake, when enabled, also change the status of d7 (see table 8 in the register tables section). debounce register (0x02) the debounce register sets the time for each debounce cycle, as well as setting whether the gpo ports are enabled or disabled. bits d0Cd4 set the debounce time in increments of 1ms starting at 9ms and ending at 40ms (see table 9 in the register tables section). bits d5, d6, and d7 set which of the gpo ports is enabled. note the gpo ports are enabled only in the combinations shown in table 9, from all disabled to all enabled. key-switch interrupt register (0x03) the interrupt register contains information related to the settings of the interrupt request function, as well as the status of the intk output, which can also be configured as a gpo. if bits d0Cd7 are set to 0x00, the intk output is configured as a gpo that is controlled by bit d1 in the port register. there are two types of interrupts, the fifo- based interrupt and time-based interrupt. set bits d0Cd4 to assert interrupts at the end of the selected number of debounce cycles following a key event (see table 10 in the register tables section). this number ranges from 1C31 debounce cycles. setting bits d7, d6, and d5 set the fifo-based interrupt when there are 2C14 key events stored in the fifo. both interrupts can be configured simultaneously and intk asserts depending on which condition is met first. intk deasserts depending on the status of bit d5 in the configuration register. ports register (0x04) the ports register sets the values of port2Cport7 and the intk port, when configured, as open-drain gpos. table 2. key-switch mapping * these columns can be configured as gpos. pin col0 col1 col2* col3* col4* col5* col6* col7* row0 key 0 key 8 key 16 key 24 key 32 key 40 key 48 key 56 row1 key 1 key 9 key 17 key 25 key 33 key 41 key 49 key 57 row2 key 2 key 10 key 18 key 26 key 34 key 42 key 50 key 58 row3 key 3 key 11 key 19 key 27 key 35 key 43 key 51 key 59 row4 key 4 key 12 key 20 key 28 key 36 key 44 key 52 key 60 row5 key 5 key 13 key 21 key 29 key 37 key 45 key 53 key 61 row6 key 6 key 14 key 22 key 30 key 38 key 46 key 54 key 62 row7 key 7 key 15 key 23 key 31 key 39 key 47 key 55 key 63 i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 ______________________________________________________________________________________ 11 the settings in this register are ignored for ports not con - figured as gpos, and a read from this register returns the values stored in the register (see table 11 in the register tables section). autorepeat register (0x05) the max7360 autorepeat feature notifies the host that at least one key has been pressed for a continuous period. the autorepeat register enables or disables this feature, sets the time delay after the last key event before the key repeat code (0x7e) is entered into the fifo, and sets the frequency at which the key-repeat code is entered into the fifo thereafter. bit d7 specifies whether the auto - repeat function is enabled with 0 denoting autorepeat disabled, and 1 denoting autorepeat enabled. bits d0C d3 specify the autorepeat delay in terms of debounce cycles ranging from 8C128 debounce cycles (see table 12 in the register tables section). bits d4, d5, and d6 specify the autorepeat rate or frequency ranging from 4C32 debounce cycles. when autorepeat is enabled, holding the key pressed results in a key-repeat event that is denoted by 0x7e. the key being pressed does not show up again in the fifo. only one autorepeat code is entered into the fifo, regardless of the number of keys pressed. the auto - repeat code continues to be entered in the fifo at the frequency set by bits d[4:6] until another key event is recorded. following the key-release event, if any keys are still pressed, the max7360 restarts the autorepeat sequence. autosleep register (0x06) autosleep puts the max7360 in sleep mode to draw minimal current. when enabled, the max7360 enters sleep mode if no keys are pressed for the autosleep time (see table 13 in the register tables section). key-switch sleep mode in sleep mode, the max7360 draws minimal current. switch-matrix current sources are turned off and pulled up to v cc . when autosleep is enabled, key-switch inactivity for a period longer than the autosleep time puts the part into sleep mode (fifo data is maintained). writing a 1 to d7 in the configuration register, or a key - press, can take the max7360 out of sleep mode. bit d7 in the configuration register gives the sleep-mode status and can be read any time. the fifo data is maintained while in sleep mode. autowake keypresses initiate autowake and the max7360 goes into operating mode. keypresses that autowake the max7360 are not lost. when a key is pressed while the max7360 is in sleep mode, all analog circuitry, including switch-matrix current sources, turn on in 2ms. the initial key needs to be pressed for 2ms plus the debounce time to be stored in the fifo. write a 0 to d1 in the configura - tion register (0x01) to disable autowakeup. gpios the max7360 has eight gpio ports with led control functions. the ports can be used as logic inputs, logic outputs, or constant-current pwm led drivers. in addi - tion, port7 and port6 can function as a rotary switch input pair. when in pwm mode, the ports are set up to start their pwm cycle in 45 n phase increments. this prevents large current spikes on the led supply voltage when driving multiple leds. gpio global configuration register (0x40) the gpio global configuration register controls the main settings for the eight gpios (see table 14 in the register tables section). bit d7 enables port[7:6] as inputs for a rotary switch. bit d5 enables interrupt generation for i 2 c timeouts. d4 is the main enable/shutdown bit for the gpios. d3 func - tions as a software reset for the gpio registers (0x40 to 0x5f). bits d[2:0] set the fade in/out time for the gpios configured as constant-current sinks. gpio control register (0x41) the gpio control register configures each port as either an input or an output (see table 15 in the register tables section). all gpios allow individual configurations, and power up as inputs. enabling rotary switch mode auto - matically sets d7 and d6 as inputs. the ports consume additional current if their inputs are left undriven. gpio debounce configuration register (0x42) the gpio debounce configuration register sets the amount of time a gpio must be held for the max7360 to register a logic transition (see table 16 in the register tables section). the gpio debounce setting is inde - pendent of the key-switch debounce setting. five bits (d[4:0]) set 32 possible debounce times from 9ms up to 40ms. i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 12 _____________________________________________________________________________________ gpio constant-current setting register (0x43) the gpio constant-current setting register sets the global constant-current amount (see table 17 in the register tables section). bits d1 and d0 set the global current values from 5ma up to 20ma. gpio output mode register (0x44) the gpio output mode register sets an output as either a constant-current or non-constant-current output for port[7:0] (see table 18 in the register tables section ). outputs are configured as constant-current outputs by default to prevent accidental loading of an led across an unregulated output. the constant-current circuits automatically turn off when not in use to reduce current consumption. common pwm register (0x45) the common pwm register stores the common constant- current output pwm duty cycle (see table 19 in the register tables section). the values stored in this register translate over to a pwm duty cycle in the same manner as the individual pwm registers (0x50 to 0x57). ports can use their own individual pwm value, or the common pwm value. write to this register to change the duty cycle of several ports at once. rotary switch configuration register (0x46) the rotary switch configuration register stores rotary switch settings for port7 and port6 (see table 20 in the register tables section). d7 determines whether switch counts or a time delay will trigger an interrupt if enabled. d[6:4] set the count or time amount to wait before sending an interrupt. bits d[3:0] set the debounce cycle time for the rotary switch inputs. debounce time ranges from 0 to 15ms. i 2 c timeout flag register (0x48) (read only) the i 2 c timeout flag register contains a single bit (d0), which indicates if an i 2 c timeout has occurred (see table 21 in the register tables section). read this register to clear an i 2 c timeout initiated interrupt. gpio input register (0x49) (read only) the gpio input register contains the input data for all of the gpios (see table 22 in the register tables section). ports configured as outputs are read as high. there is one debounce period delay prior to detecting a transition on the input port. this prevents a false interrupt from occurring when changing a port from an output to an input. the gpio input register reports the state of all input ports regardless of any interrupt mask settings. ports configured as an input have a 2 f a internal pullup to v cc for port[5:0] and a 10 f a internal pullup to v cc for port[7:6]. rotary switch count register (0x4a) (read only) the max7360 keeps a count of the rotary switch rotations in twos compliment format (see table 23 in the register tables section). the register values wrap around as the count value switches from a positive to a negative value and back again. the count resets to zero after an i 2 c read to this register. port0Cport7 individual pwm ratio registers (0x50 to 0x57) each port has an individual pwm ratio register (0x50 to 0x57, see table 24 in the register tables section). use values 0x00 to 0xfe in these registers to configure the number of cycles out of 256 the output sinks current (led is on), from 0 cycles to 254 cycles. use 0xff to have an output continuously sink current (always on). for applications requiring multiple ports to have the same intensity, program a particular ports configuration register (0x58 to 0x5f) to use the common pwm register (0x45). new pwm settings take place at the beginning of a pwm cycle, to allow changes from common intensity to individual intensity with no interruption in the pwm cycle. port0Cport7 configuration registers (0x58 to 0x5f) registers 0x58 to 0x5f set individual configurations for each port (see table 25 in the register tables section). bits d7 and d6 determine the interrupt settings for the inputs. interrupts can assert upon detection of a logic transition, a rising edge, or not at all. d5 sets the ports pwm setting to either the common or individual pwm setting. bits d[4:2] enable and set the ports individual blink period from 0 to 4096ms. bits d1 and d0 set a ports blink duty cycle. fading set the fade cycle time in the gpio global configuration register (0x40) to a non-zero value to enable fade in/out (see table 14 in the register tables section). fade in increases an leds pwm intensity in 16 even steps from zero to its stored value. fade out decreases an leds pwm intensity in 16 even steps from its current value to zero. fading occurs automatically in any of the following scenarios: 1) change the common pwm register value from any value to zero to cause all ports using the common pwm register settings to fade out. no ports using individual pwm settings are affected. 2) change the common pwm register value to any value from zero to cause all ports using the common pwm register settings to fade in. no ports using indi - vidual pwm settings are affected. 3) put the part out of shutdown to cause all ports to fade in. changing an individual pwm intensity during fade i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 ______________________________________________________________________________________ 13 in automatically cancels that ports fade and immedi - ately output at its newly programmed intensity. 4) put the part into shutdown to cause all ports to fade out. changing an individual pwm intensity during fade out automatically cancels that ports fade and immediately turns off. blink each port has its own blink control settings through reg - isters 0x58 to 0x5f (see table 25 in the register tables section). the blink period ranges from 0 (blink disabled) to 4.096s. settable blink duty cycles range from 6.25% to 50%. all blink periods start at the same pwm cycle for synchronized blinking between multiple ports. gpio port interrupts (inti) three possible sources generate inti : i 2 c timeout, gpios configured as inputs, and the rotary switch (registers 0x48, 0x49, and 0x4a). read the respective data/status registers for each type of interrupt to clear inti . set register 0x46 for rotary switch-based interrupts. set registers 0x58 to 0x5f for individual gpi-based inter - rupts. if multiple sources generate the interrupt, all the related status registers must be read to clear inti. rotary switch the max7360 can accept a 2-bit rotary switch inputs on port6 and port7. rotation of the switch in a clockwise direction increments the count. enable rotary switch mode from the gpio global configuration register (0x40). several settings for port6 and port7 occur during rotary switch mode: 1) each port has a 10 f a pullup to v cc . 2) register 0x46 sets the debounce time. 3) a debounced rising edge on port6 while port7 is high decreases the count. 4) a debounced rising edge on port6 while port7 is low increases the count. for more details, see figure 1. serial interface figure 2 shows the 2-wire serial interface timing details. serial addressing the max7360 operates as a slave that sends and receives data through an i 2 c-compatible 2-wire inter - face. the interface uses a serial-data line (sda) and a serial-clock line (scl) to achieve bidirectional com - munication between master(s) and slave(s). a master (typically a microcontroller) initiates all data transfers to and from the max7360 and generates the scl clock that synchronizes the data transfer. the max7360s sda line operates as both an input and an open-drain output. a pullup resistor, typically 4.7k i, figure 2. 2-wire serial interface timing details figure 1. rotary switch input signal timing sda scl t hd, sta t low t high t r t f t su, dat t su, sta t su, sto t buf t hd, sta t hd, dat start condition stop condition start condition repeated start condition t f t f, tx t r port7 port6 port7 port6 increment decrement rotary switch debounce i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 14 _____________________________________________________________________________________ is required on sda. the max7360s scl line operates only as an input. a pullup resistor is required on scl if there are multiple masters on the 2-wire interface, or if the master in a single-master system has an open-drain scl output. each transmission consists of a start (s) condition (figure 3) sent by a master, followed by the max7360 7-bit slave address plus r/ w bit, a register address byte, one or more data bytes, and finally, a stop (p) condition. start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmission with a start condition by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, it issues a stop condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission. bit transfer one data bit is transferred during each clock pulse (figure 4). the data on sda must remain stable while scl is high. acknowledge the acknowledge bit is a clocked 9th bit (figure 5), which the recipient uses to handshake receipt of each byte of data. thus, each byte transferred effectively requires 9 bits. the master generates the 9th clock pulse, and the recipient pulls down sda during the acknowledge clock pulse; therefore, the sda line is stable low during the high period of the clock pulse. when the master is transmitting to the max7360, the max7360 generates the acknowledge bit because the max7360 is the recipi - ent. when the max7360 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. figure 3. start and stop conditions figure 4. bit transfer table 3. 2-wire interface address map pin ad0 device address a7 a6 a5 a4 a3 a2 a1 a0 gnd 0 1 1 1 0 0 0 r/w v cc 0 1 1 1 0 1 0 r/w sda 0 1 1 1 1 0 0 r/w scl 0 1 1 1 1 1 0 r/w sda scl start condition stop condition s p sda scl data line stable; data valid change of data allowed i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 ______________________________________________________________________________________ 15 figure 5. acknowledge figure 6. slave address slave addresses the max7360 has a 7-bit long slave address (figure 6). the bit following a 7-bit slave address is the r/ w bit, which is low for a write command and high for a read command. the first 4 bits (msbs) of the max7360 slave address are always 0111. slave address bits a3, a2, and a1 correspond, by the matrix in table 3, to the states of the device address input ad0, and a0 corresponds to the r/w bit. the ad0 input can be connected to any of four signals (gnd, v cc , sda, or scl), giving four possible slave address pairs and allowing up to four max7360 devices to share the bus. because sda and scl are dynamic signals, care must be taken to ensure that ad0 transitions no sooner than the signals on sda and scl. the max7360 monitors the bus continuously, waiting for a start condition, followed by its slave address. when the max7360 recognizes its slave address, it acknowledges and is then ready for continued communication. bus timeout the max7360 features a 20ms minimum bus timeout on the 2-wire serial interface, largely to prevent the max7360 from holding the sda i/o low during a read transaction should the scl lock up for any reason before a serial transaction is completed. bus timeout operates by causing the max7360 to internally terminate a serial figure 7. command byte received figure 8. command and single data byte received scl sda by transmitter clock pulse for acknowledge start condition sda by receiver 1 2 8 9 s sda scl 0 1 1 a3 a2 a1 1 msb lsb ack r/w s a a p 0 slave address command byte d7 d6 d5 d4 d3 d2 d1 d0 command byte is stored on receipt of acknowledge condition acknowledge from max7360 acknowledge from max7360 r/w s a a a p 0 slave address command byte data byte 1 byte autoincrement command byte address d7 d6 d5 d4 d3 d2 d1 d0 d1 d0 d3 d2 d5 d4 d7 d6 acknowledge from max7360 acknowledge from max7360 acknowledge from max7360 r/w i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 16 _____________________________________________________________________________________ transaction, either read or write, if scl low exceeds 20ms. after a bus timeout, the max7360 waits for a valid start condition before responding to a consecutive transmission. this feature can be enabled or disabled under user control by writing to the configuration register (table 8 in the register tables section). message format for writing the key-scan controller a write to the max7360 comprises the transmission of the slave address with the r/ w bit set to zero, followed by at least 1 byte of information. the first byte of information is the command byte. the command byte determines which register of the max7360 is to be written by the next byte, if received. if a stop condition is detected after the command byte is received, the max7360 takes no further action (figure 7) beyond storing the command byte. any bytes received after the command byte are data bytes. the first data byte goes into the internal register of the max7360 selected by the command byte (figure 8). if multiple data bytes are transmitted before a stop condi - tion is detected, these bytes are generally stored in subse - quent max7360 internal registers, because the command byte address generally autoincrements (table 4). message format for reading the key-scan controller the max7360 is read using the internally stored com - mand byte as an address pointer, the same way the stored command byte is used as an address pointer for a write. the pointer generally autoincrements after each data byte is read using the same rules as for a write (table 4). thus, a read is initiated by first config - uring the max7360s command byte by performing a write (figure 7). the master can now read n consecutive bytes from the max7360, with the first data byte being read from the register addressed by the initialized com - mand byte. when performing read-after-write verifica - tion, remember to reset the command bytes address, because the stored command byte address is generally autoincremented after the write (figure 9, table 4). operation with multiple masters when the max7360 is operated on a 2-wire interface with multiple masters, a master reading the max7360 uses a repeated start between the write that sets the max7360s address pointer, and the read(s) that takes the data from the location(s). this is because it is pos - sible for master 2 to take over the bus after master 1 has set up the max7360s address pointer, but before mas - ter 1 has read the data. if master 2 subsequently resets the max7360s address pointer, master 1s read can be from an unexpected location. command address autoincrementing address autoincrementing allows the max7360 to be configured with fewer transmissions by minimizing the number of times the command address needs to be sent. the command address stored in the max7360 generally increments after each data byte is written or read (table 4). autoincrement only works when doing a multiburst read or write. applications information reset from i 2 c after a catastrophic event such as esd discharge or microcontroller reset, use bit d7 of the configuration register (0x01) as a software reset for the key-switch state (the key-switch register values and fifo remain unaffected). use bit d4 of the gpio global configura - tion register (0x40) as a software reset for the gpios. figure 9. n data bytes received table 4. autoincrement rules register function address code (hex) autoincrement address (hex) keys fifo 0x00 0x00 autoshutdown 0x06 0x00 all other key switch 0x01 to 0x05 addr + 0x01 all other gpio 0x40 to 0x5f addr + 0x01 s a a a p 0 slave address command byte data byte n bytes autoincrement command byte address d7 d6 d5 d4 d3 d2 d1 d0 d1 d0 d3 d2 d5 d4 d7 d6 acknowledge from max7360 acknowledge from max7360 acknowledge from max7360 r/w i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 ______________________________________________________________________________________ 17 figure 10. ghost-key phenomenon figure 11. valid three-key combinations ghost-key elimination ghost keys are a phenomenon inherent with key-switch matrices. when three switches located at the corners of a matrix rectangle are pressed simultaneously, the switch that is located at the last corner of the rectangle (the ghost key) also appears to be pressed. this occurs because the potentials at the two sides of the ghost-key switch are identical due to the other three connections the switch is electrically shorted by the combination of the other three switches (figure 10). because the key appears to be pressed electrically, it is impossible to detect which of the four keys is the ghost key. the max7360 employs a proprietary scheme that detects any three-key combination that generates a fourth ghost key, and does not report the third key that causes a ghost-key event. this means that although ghost keys are never reported, many combinations of three keys are effectively ignored when pressed at the same time. applications requiring three-key combinations (such as i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 18 _____________________________________________________________________________________ esd protection all of the max7360 pins meet the 2kv human body model esd tolerances. key-switch inputs and gpios meet iec 61000-4-2 esd protection. the iec test stresses consist of 10 consecutive esd discharges per polarity, at the maximum specified level and below (per iec 61000-4-2). test criteria include: 1) the powered device does not latch up during the esd discharge event. 2) the device subsequently passes the final test used for prescreening. tables 5 and 6 are from the iec 61000-4-2: edition 1.1 1999-05: electromagnetic compatibility (emc) testing and measurement techniqueselectrostatic discharge immunity test . table 6. esd waveform parameters table 5. esd test levels x = open level. the level has to be specified in the dedicated equipment specification. if higher voltages than those shown are specified, special test equipment could be needed. level indicated voltge (kv) first peak of current discharge 10% (a) rise time (t r ) with discharge switch (ns) current ( 30%) at 30ns (a) current ( 30%) at 60ns (a) 1 2 7.5 0.7 to 1 4 2 2 4 15 0.7 to 1 8 4 3 6 22.5 0.7 to 1 12 6 4 8 30 0.7 to 1 16 8 1acontact discharge 1bair-gap discharge level test voltage (kv) level test voltage (kv) 1 2 1 2 2 4 2 4 3 6 3 8 4 8 4 10 x special x special i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 ______________________________________________________________________________________ 19 table 7. keys fifo register format (0x00) registe r tables special function keys fifo register data d7 d6 d5 d4 d3 d2 d1 d0 the key number indicated by d5:d0 is a key event. d7 is always for a key press of key 62 and key 63. when d7 is 0, the key read is the last data in the fifo. when d7 is 1, there is more data in the fifo. when d6 is 1, key data read from fifo is a key release. when d6 is 0, key data read from fifo is a key press. fifo empty flag key release flag x x x x x x fifo is empty. 0 0 1 1 1 1 1 1 fifo is overflow. continue to read data in fifo 0 1 1 1 1 1 1 1 key 63 is pressed. read one more time to determine whether there is more data in fifo. 1 0 1 1 1 1 1 1 key 63 is released. read one more time to determine whether there is more data in fifo. 1 1 1 1 1 1 1 1 key repeat. indicates the last data in fifo. 0 0 1 1 1 1 1 0 key repeat. indicates more data in fifo. 0 1 1 1 1 1 1 0 key 62 is pressed. read one more time to determine whether there is more data in fifo. 1 0 1 1 1 1 1 0 key 62 is released. read one more time to determine whether there is more data in fifo. 1 1 1 1 1 1 1 0 i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 20 _____________________________________________________________________________________ table 8. configuration register format (0x01) table 9. debounce register format (0x02) register bit description value function default value d7 sleep x (when 0x40 d4 = 1) key-switch operating mode. key switches always remain active when constant-current pwm is enabled (bit 4 of register 0x40 is high) regardless of autosleep, autowakeup, or an i 2 c write to this bit. 0 0 (when 0x40 d4 = 0) key-switch sleep mode. the entire chip is shut down. when constant-current pwm is disabled (bit 4 of register 0x40 is low), i 2 c write, autosleep, and autowakeup all can change this bit. this bit can be read back by i 2 c any time for current status. 1 (when 0x40 d4 = 0) key-switch operating mode d6 reserved 0 0 d5 interrupt 0 intk cleared when fifo is empty 0 1 intk cleared after host read. in this mode, i 2 c should read the fifo until interrupt condition is removed or further int may be lost. d4 reserved 0 0 d3 key-release enable 0 disable key releases 1 1 enable key releases d2 reserved 0 0 d1 autowakeup enable 0 disable keypress wakeup 1 1 enable keypress wakeup d0 timeout disable 0 i 2 c timeout enabled 0 1 i 2 c timeout disabled register description register data d7 d6 d5 d4 d3 d2 d1 d0 ports enable debounce time debounce time is 9ms x x x 0 0 0 0 0 debounce time is 10ms x x x 0 0 0 0 1 debounce time is 11ms x x x 0 0 0 1 0 debounce time is 12ms x x x 0 0 0 1 1 . . . debounce time is 37ms x x x 1 1 1 0 0 debounce time is 38ms x x x 1 1 1 0 1 debounce time is 39ms x x x 1 1 1 1 0 debounce time is 40ms x x x 1 1 1 1 1 gpo ports disabled (full key-scan functionality) 0 0 0 x x x x x gpo port 7 enabled 0 0 1 x x x x x gpo ports 7 and 6 enabled 0 1 0 x x x x x i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 ______________________________________________________________________________________ 21 table 10. key-switch interrupt register format (0x03) table 9. debounce register format (0x02) (continued) register description register data d7 d6 d5 d4 d3 d2 d1 d0 ports enable debounce time gpo ports 7, 6, and 5 enabled 0 1 1 x x x x x gpo ports 7, 6, 5, and 4 enabled 1 0 0 x x x x x gpo ports 7, 6, 5, 4, and 3 enabled 1 0 1 x x x x x gpo ports 7, 6, 5, 4, 3, and 2 enabled 1 1 x x x x x x power-up default setting 1 1 1 1 1 1 1 1 register description register data d7 d6 d5 d4 d3 d2 d1 d0 fifo-based intk time-based intk intk used as gpo 0 0 0 0 0 0 0 0 fifo-based intk disabled 0 0 0 not all zero intk asserts every debounce cycle 0 0 0 0 0 0 0 1 intk asserts every 2 debounce cycles 0 0 0 0 0 0 1 0 . . . intk asserts every 29 debounce cycles 0 0 0 1 1 1 0 1 intk asserts every 30 debounce cycles 0 0 0 1 1 1 1 0 intk asserts every 31 debounce cycles 0 0 0 1 1 1 1 1 time-based intk disabled not all zero 0 0 0 0 0 intk asserts when fifo has 4 key events 0 0 1 0 0 0 0 0 intk asserts when fifo has 6 key events 0 1 0 0 0 0 0 0 intk asserts when fifo has 8 key events 0 1 1 0 0 0 0 0 . . . intk asserts when fifo has 14 key events 1 1 1 0 0 0 0 0 both time-based and fifo-based interrupts active not all zero not all zero power-up default setting 0 0 0 0 0 0 0 0 i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 22 _____________________________________________________________________________________ table 11. ports register format (0x04) register bit description value function default value d7 port 7 control 0 clear port 7 low 1 1 set port 7 high (high impedance) d6 port 6 control 0 clear port 6 low 1 1 set port 6 high (high impedance) d5 port 5 control 0 clear port 5 low 1 1 set port 5 high (high impedance) d4 port 4 control 0 clear port 4 low 1 1 set port 4 high (high impedance) d3 port 3 control 0 clear port 3 low 1 1 set port 3 high (high impedance) d2 port 2 control 0 clear port 2 low 1 1 set port 2 high (high impedance) d1 intk port control 0 clear port intk low 1 1 set port intk high (high impedance) d0 reserved 0 0 i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 ______________________________________________________________________________________ 23 table 12. autorepeat register format (0x05) register description register data d7 d6 d5 d4 d3 d2 d1 d0 enable autorepeat rate autorepeat delay autorepeat is disabled 0 x x x x x x x autorepeat is enabled 1 autorepeat rate autorepeat delay key-switch autorepeat delay is 8 debounce cycles 1 x x x 0 0 0 0 key-switch autorepeat delay is 16 debounce cycles 1 x x x 0 0 0 1 key-switch autorepeat delay is 24 debounce cycles 1 x x x 0 0 1 0 . . . key-switch autorepeat delay is 112 debounce cycles 1 x x x 1 1 0 1 key-switch autorepeat delay is 120 debounce cycles 1 x x x 1 1 1 0 key-switch autorepeat delay is 128 debounce cycles 1 x x x 1 1 1 1 key-switch autorepeat frequency is 4 debounce cycles 1 0 0 0 x x x x key-switch autorepeat frequency is 8 debounce cycles 1 0 0 1 x x x x key-switch autorepeat frequency is 12 debounce cycles 1 0 1 0 x x x x . . . key-switch autorepeat frequency is 32 debounce cycles 1 1 1 1 x x x x power-up default setting 0 0 0 0 0 0 0 0 i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 24 _____________________________________________________________________________________ table 13. autosleep register format (0x06) table 14. gpio global configuration register (0x40) register register data autosleep register reserved autoshutdown time d7 d6 d5 d4 d3 d2 d1 d0 no autosleep 0 0 0 0 0 0 0 0 autosleep for (ms) 8192 0 0 0 0 0 0 0 1 4096 0 0 0 0 0 0 1 0 2048 0 0 0 0 0 0 1 1 1024 0 0 0 0 0 1 0 0 512 0 0 0 0 0 1 0 1 256 0 0 0 0 0 1 1 0 256 0 0 0 0 0 1 1 1 power-up default settings 0 0 0 0 0 1 1 1 register bit description value function default value d7 port6/port7 rotary switch 0 port6/port7 operate as gpios 0 1 port6/port7 operate as a rotary switch input d6 reserved 0 0 d5 i 2 c timeout interrupt enable 0 disabled 0 1 inti is asserted when i 2 c bus times out. inti is deasserted when a read is performed on the i 2 c timeout flag register (0x48). d4 gpio enable 0 pwm, constant-current circuits, and gpis are shut down. gpo values depend on their setting. register 0x41 to 0x5f values are stored and cannot be changed. the entire part is shut down if the key switches are in sleep mode (d7 of register 0x01). 0 1 normal gpio operation. pwm, constant-current circuits, and gpios are enabled regardless of key-switch sleep mode state (see table 8). d3 gpio reset 0 normal operation 0 1 return all gpio registers (registers 0x40 to 0x5f) to their por value. this bit is momentary and resets itself to 0 after the write cycle. d[2:0] fade in/out time 000 no fading 000 xxx pwm intensity ramps up (down) between the common pwm value and 0% duty cycle in 16 steps over the following time period: d[2:0] = 001 = 256ms d[2:0] = 010 = 512ms d[2:0] = 011 = 1024ms d[2:0] = 100 = 2048ms d[2:0] = 101 = 4096ms d[2:0] = 110/111 = undefined i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 ______________________________________________________________________________________ 25 table 15. gpio control register (0x41) table 16. gpio debounce configuration register (0x42) register bit description value function default value d7 port7 0 port is an input 0 1 port is an output d6 port6 0 port is an input 0 1 port is an output d5 port5 0 port is an input 0 1 port is an output d4 port4 0 port is an input 0 1 port is an output d3 port3 0 port is an input 0 1 port is an output d2 port2 0 port is an input 0 1 port is an output d1 port1 0 port is an input 0 1 port is an output d0 port0 0 port is an input 0 1 port is an output register description register data d7 d6 d5 d4 d3 d2 d1 d0 reserved debounce time power-up default setting debounce time is 9ms 0 0 0 0 0 0 0 0 debounce time is 10ms 0 0 0 0 0 0 0 1 debounce time is 11ms 0 0 0 0 0 0 1 0 debounce time is 12ms 0 0 0 0 0 0 1 1 . . . debounce time is 37ms 0 0 0 1 1 1 0 0 debounce time is 38ms 0 0 0 1 1 1 0 1 debounce time is 39ms 0 0 0 1 1 1 1 0 debounce time is 40ms 0 0 0 1 1 1 1 1 i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 26 _____________________________________________________________________________________ table 17. gpio constant-current setting register (0x43) table 18. gpio output mode register (0x44) table 19. common pwm register (0x45) register bit description value function default value d[7:6] reserved 11 set always as 11 11 d[5:2] reserved 0000 0000 d[1:0] constant- current setting 00 constant current is 5ma 00 01 constant current is 6.67ma 10 constant current is 10ma 11 constant current is 20ma register bit description value function default value d7 port7 0 port is a constant-current open-drain output 0 1 port is a non-constant-current open-drain output d6 port6 0 port is a constant-current open-drain output 0 1 port is a non-constant-current open-drain output d5 port5 0 port is a constant-current open-drain output 0 1 port is a non-constant-current open-drain output d4 port4 0 port is a constant-current open-drain output 0 1 port is a non-constant-current open-drain output d3 port3 0 port is a constant-current open-drain output 0 1 port is a non-constant-current open-drain output d2 port2 0 port is a constant-current open-drain output 0 1 port is a non-constant-current open-drain output d1 port1 0 port is a constant-current open-drain output 0 1 port is a non-constant-current open-drain output d0 port0 0 port is a constant-current open-drain output 0 1 port is a non-constant-current open-drain output register description register data d7 d6 d5 d4 d3 d2 d1 d0 common pwm power-up default setting (common pwm ratio is 0/256) 0 0 0 0 0 0 0 0 common pwm ratio is 1/256 0 0 0 0 0 0 0 1 common pwm ratio is 2/256 0 0 0 0 0 0 1 0 common pwm ratio is 3/256 0 0 0 0 0 0 1 1 . . . i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 ______________________________________________________________________________________ 27 table 19. common pwm register (0x45) (continued) table 20. rotary switch configuration register (0x46) register description register data d7 d6 d5 d4 d3 d2 d1 d0 int type counts/cycles debounce cycle time no debounce time x x x x 0 0 0 0 debounce time is 1ms x x x x 0 0 0 1 debounce time is 2ms x x x x 0 0 1 0 debounce time is 3ms x x x x 0 0 1 1 . . . debounce time is 15ms x x x x 1 1 1 1 no interrupt generated by rotary switch x 0 0 0 x x x x inti asserted when rotary switch count = 1 0 0 0 1 x x x x inti asserted when rotary switch count = 2 0 0 1 0 x x x x inti asserted when rotary switch count = 3 0 0 1 1 x x x x . . . inti asserted when rotary switch count = 7 0 1 1 1 x x x x inti asserted 25ms after first debounced event 1 0 0 1 x x x x inti asserted 50ms after first debounced event 1 0 1 0 x x x x inti asserted 75ms after first debounced event 1 0 1 1 x x x x . . . inti asserted 175ms after first debounced event 1 1 1 1 x x x x power-up default setting 0 0 0 0 0 0 0 0 register description register data d7 d6 d5 d4 d3 d2 d1 d0 common pwm common pwm ratio is 252/256 1 1 1 1 1 1 0 0 common pwm ratio is 253/256 1 1 1 1 1 1 0 1 common pwm ratio is 254/256 1 1 1 1 1 1 1 0 common pwm ratio is 256/256 (100% duty cycle) 1 1 1 1 1 1 1 1 i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 28 _____________________________________________________________________________________ table 21. i 2 c timeout flag register (0x48) (read only) table 22. gpio input register (0x49) (read only) table 23. rotary switch count register (0x4a) (read only) register bit description value function default value d[7:1] reserved 0000000 0000000 d0 i 2 c timeout flag 0 no i 2 c timeout has occurred since last read or por 0 1 i 2 c timeout has occurred since last read or por. this bit is reset to zero when a read is performed on this register. i 2 c timeouts must be enabled for this function to work (see table 8). register description register data d7 d6 d5 d4 d3 d2 d1 d0 cycle count cycle count in twos complement (see the rotary switch configuration register (0x46) section) x x x x x x x x register bit description value function default value d7 port7 0 port is input low 1 1 port is input high d6 port6 0 port is input low 1 1 port is input high d5 port5 0 port is input low 1 1 port is input high d4 port4 0 port is input low 1 1 port is input high d3 port3 0 port is input low 1 1 port is input high d2 port2 0 port is input low 1 1 port is input high d1 port1 0 port is input low 1 1 port is input high d0 port0 0 port is input low 1 1 port is input high i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 ______________________________________________________________________________________ 29 table 24. port0Cport7 individual pwm ratio registers (0x50 to 0x57) table 25. port0Cport7 configuration registers (0x58 to 0x5f) register description register data d7 d6 d5 d4 d3 d2 d1 d0 port pwm power-up default setting (port pwm ratio is 0/256) 0 0 0 0 0 0 0 0 port pwm ratio is 1/256 0 0 0 0 0 0 0 1 port pwm ratio is 2/256 0 0 0 0 0 0 1 0 port pwm ratio is 3/256 0 0 0 0 0 0 1 1 . . . port pwm ratio is 252/256 1 1 1 1 1 1 0 0 port pwm ratio is 253/256 1 1 1 1 1 1 0 1 port pwm ratio is 254/256 1 1 1 1 1 1 1 0 port pwm ratio is 256/256 (100% duty cycle) 1 1 1 1 1 1 1 1 register bit description value function default value d7 interrupt mask 0 interrupt is not masked 0 1 interrupt is masked. port7 interrupt mask is ignored when the device is configured for rotary switch input. d6 edge/level detect 0 rising edge-triggered interrupts interrupts only occur when the gpio port is configured as an input 0 1 rising or falling edge- triggered interrupts d5 common pwm 0 port uses individual pwm intensity register to set the pwm ratio 0 1 port uses common pwm intensity register to set the pwm ratio d[4:2] blink period 000 port does not blink 000 001 port blink period is 256ms 010 port blink period is 512ms 011 port blink period is 1024ms 100 port blink period is 2048ms 101 port blink period is 4096ms 110/111 undefined d[1:0] blink-on time 00 led is on for 50% of the blink period 00 01 led is on for 25% of the blink period 10 led is on for 12.5% of the blink period 11 led is on for 6.25% of the blink period i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 30 _____________________________________________________________________________________ pin configurations max7360 tqfn top view 35 36 34 33 12 11 13 row1 row3 gnd row4 row5 14 row0 n.c. gnd inti ad0 i.c. n.c. intk scl 1 2 port3 4 5 6 7 27 28 29 30 26 ep* + 24 23 22 gnd port4 col6 col5 col4 gnd row2 v cc 3 25 37 port5 col3 38 39 40 port6 port7 n.c. col2 col1 col0 *ep = exposed pad, connect ep to ground. port2 32 15 col7 port1 31 16 17 18 19 20 n.c. row6 row7 n.c. sda 8 9 10 21 port0 max7360 top view bumps in bottom wlp (2.67mm x 2.67mm) i.c. ad0 v cc row4 port1 port0 n.c. row5 port2 port5 row7 port4 gnd row2 intk a1 b1 c1 d1 a2 b2 c2 d2 a3 b3 c3 d3 a4 b4 c4 d4 port3 row6 col6 sda col0 gnd col4 col5 col3 e1 f1 e2 f2 e3 f3 e4 f4 port7 gnd gnd row0 row1 row3 inti a5 b5 c5 d5 a6 b6 c6 d6 port6 col1 col2 scl col7 e5 f5 e6 f6 i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 ______________________________________________________________________________________ 31 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages. chip information process: bicmos package type package code document no. 40 tqfn-ep t4055+1 21-0140 36 wlp w362a2+1 21-0301 typical application circuit port6 port7 port5 port4 port3 port2 port1 port0 max7360 row7 row6 row5 row4 row3 row2 row1 row0 sda scl inti intk ad0 col0 col1 col2 col3 col4 col5 col6 col7 gnd v cc scl sda inti intk +1.8v gnd c v cc +14v +3.3v +14v +3.3v key 0 key 1 key 2 key 3 key 4 key 5 key 6 key 7 key 8 key 9 key 10 key 11 key 12 key 13 key 14 key 15 key 16 key 17 key 18 key 19 key 20 key 21 key 22 key 23 key 24 key 25 key 26 key 27 key 28 key 29 key 30 key 31 key 32 key 33 key 34 key 35 key 36 key 37 key 38 key 39 key 40 key 41 key 42 key 43 key 44 key 45 key 46 key 47 i 2 c-interfaced key-switch controller and led driver/gpios with integrated esd protection max7360 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 32 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 4/09 initial release 1 8/10 updated absolute maximum ratings and notes 7 and 8 (now notes 6 and 7) in electrical characteristics 2, 3, 4 |
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